International Journal of Neural Systems, Vol. 7, Nos. 6 (1997) 697
© World Scientific Publishing Company
VLSI NEURAL SYSTEM ARCHITECTURE FOR FINITE RING RECURSIVE REDUCTION



VLSI NEURAL SYSTEM ARCHITECTURE FOR FINITE RING RECURSIVE REDUCTION

D. ZHANG1,2
Department of Computer Science,
City University of Hong Kong, Tat Chee Avenue,
Kowloon, Hong Kong

G. A. JULLIEN1
VLSI Research Group,
Department of Electrical Engineering,
University of Windsor, Windsor, Ontario, Canada N9B 3P4
 1Senior member, IEEE
2E-mail: dapeng@cs.cityu.edu.hk

The use of neural-like networks to implement finite ring computations has been presented in a previous paper.1 This paper develops efficient VLSI neural system architecture for the finite ring recursive reduction (FRRR), including modulo reduction, MSB carry iteration and feedforward processing. These techniques deal with the basic principles involved in constructing a FRRR, and their implementations are efficiently matched to the VLSI medium. Compared with the other structure models for finite ring computation (e.g. modification of binary arithmetic logic and bit-steered ROM's), the FRRR structure has the lowest area complexity in silicon while maintaining a high throughput rate. Examples of several implementations are used to illustrate the effectiveness of the FRRR architecture.





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